In the past few decades, the technique of scaling down MOS devices has greatly improved the performance and speed of CMOS integrated circuits. The law of the number of transistors per unit area on a chip being doubled every 18 months as described by the Moore's Law is still true today. With the increasing development in the integrated circuit technique, during the continuous scaling down of the CMOS technique, the power consumption and working voltage of MOS devices thereof cannot keep scaling down at the same scale, and various parasitic effects, performance deterioration and reliability issues are becoming more and more serious. Especially when the channel is reduced to a nanometer range, the bulk silicon MOS device is close to its physical limit, thus many serious problems like short channel effect, low mobility and reduced gate dielectric thickness occur. Therefore, with the reduction in channel size, one of the challenges faced by the conventional bulk silicon CMOS technique is to maintain a high drive current with a reasonable drain current while controlling the short channel effect of the device. However, at the present technological level, the thickness of nitrogen oxide, polysilicon and gate-oxide, for example, has already reached the limit of scaling down, and due to dielectric current leakage, device power consumption and the tunneling effect of thin layer gate oxide, further reduction in size is greatly restricted and cannot promote a continuous improvement of the device performance. Based on the above-described background, it is important for the development of the integrated circuit technique to develop a new device structure that can suppress the short channel effect during the size reduction process, increase the driving capability of the channel and increase integration so as to breakthrough the channel size reduction limitation.
Another method of overcoming the limitation of the Moore's Law is to integrate devices and circuits of different functions, for example, MPU, image processing, memory (SRAM, flash memory, DRAM), logic processor, DSP, signal mixer, radio frequency (RF) and peripheral function components, thereby realizing the advantages obtained through system integration, such as high performance, low price, small contact area and volume, excellent power management. Such kind of integration technique is called System in a Package (SIP). System in a Package can enclose all or most of the electronic functions, which may be a system or subsystem, or components, circuits and elements, into one package body, besides, the System in a Package is not only a package of a single chip or multiple chips, but it may also include such passive devices as capacitors and resistors. For example, the System in a Package at present can integrate microprocessors, memories (e.g. Flash, SRAM and DRAM), sensors, resistors, capacitors and inductors into one package that accommodate a plurality of chips. But the SIP structure is facing a serious problem in heat dissipating for the following reasons: 1) the stacked chips will generate more heat, but the area of dissipation is not accordingly increased, which results in a great increase in the density of heat generation; 2) the multiple-chip package has the original area of dissipation retained, but the heat sources abut against each other and the heat coupling is enhanced, which results in more serious heat problems; 3) the passive devices built in the substrate also have certain heat problems, meanwhile, the organic or ceramic substrate has poor heat dispersion, which also results in serious heat dissipation problems; 4) the volume of the package is reducing, and the assembling density is increasing, which made the heat dissipation problem even worse, so a highly efficient heat dissipation design is needed.
In fact, the power consumption problem has always been a very important problem in the design and manufacturing of integrated circuits and MOS devices. From the early bipolar transistor circuits to the nanometer CMOS integrated circuits nowadays, power reduction has always been one of the main reasons for the changes and development to the fundamental devices and integrated circuits. Ever since the process node of the CMOS technique enters 90 nm, the drain current problem in the sub-threshold region of the MOS transistor becomes increasingly serious, the static power consumption of the CMOS circuit increases greatly, and power management becomes an important factor of consideration. When the process node is further reduced, namely, when it enters 45 nm, the gate oxide is getting thinner, the gate drain current increases, the device current leakage becomes more serious, and accordingly, the power consumption increases rapidly. At present, high performance microprocessors and computer systems are facing serious system power consumption problems which are mainly caused by the increase in the current leakage of large-scale integrated devices, the non-proportional reduction in the working voltage due to limitation by the device principle, linear increase in the number of transistors, and the corresponding power consumption of multi-functional system integration.
The main functions of an integrated circuit include the two categories of logic and storage. The logic circuits are usually built according to the Von Neumann architecture to realize the functions of controlling and changing the status, such as logic switching and computing. A logic circuit is formed by a great number of repeated MOS transistors, wherein the transistors are usually switching devices, one transistor forming one logic switch. A memory is formed by a great number of MOS transistors having storage function and/or other functional devices to store and temporarily store information. Dynamic Random Access Memory (DRAM) is an important type of memory and it usually consists of a switching transistor for controlling access of information and a capacitor for storing electric charge information, which form an information storage unit and consumes power.
To overcome the above-mentioned problems with power consumption occurred in the process of integrated circuit development, there are the following courses of action to take: (1) reducing the device working voltage, from example, from 1 volt to 0.5 volt; (2) reducing the device drain current; (3) merging the functions of the devices to reduce the total number of transistors and increasing the energy utilization efficiency of a single-transistor.
A device employing a new principle to reduce working voltage has been developed at present, namely, a tunneling transistor (TFET). The tunneling transistor makes use of the quantum tunneling mechanism and breaks the limit of thermokinetics with the sub-threshold factor ss smaller than 60 mV/dec, so the sub-threshold transition area is reduced, which results in a smaller device working voltage and a general reduction in power consumption.
Many kinds of tunneling transistor structures have been developed currently, as shown in FIG. 1. FIG. 1a shows a silicon-based homogeneous p-i-n tunneling structure, which has such characteristics as low tunneling efficiency and small drive current. The SS thereof is about 40 mV/dec and the working voltage is about 0.7V. FIG. 1b shows a silicon based heterojunction p-i-n tunneling structure, which has improved tunneling efficiency and increased drive current. The SS thereof is about 40 mV/dec and the working voltage is about 0.5V. FIG. 1c shows a narrow band homogeneous p-i-n tunneling structure, which has improved tunneling efficiency and increased drive current, with SS<<40 mV/dec and the working voltage of about 0.4V. And its reverse current leakage is large. FIG. 1d shows a silicon based homogeneous p-i-n tunneling structure with multiple gates, which has improved tunneling efficiency and increased drive current, the SS thereof is about 40 mV/dec and the working voltage is about 0.5V, and the reverse current leakage is reduced.
It can be seen that it would be significant to develop a new transistor structure that is greatly improved in working voltage, sub-threshold factor, drive current and/or reverse current leakage and so on, with respect to the present transistors (including tunneling transistors), in order to reduce power consumption of future integrated circuits.
The present invention reduces the total power consumption of the device, and even the circuit, based on the structure improvement and function merging of the tunneling transistor.